1. Field of the Invention
The present invention relates generally to semiconductor memories and more particularly to non-volatile read-only memories which are programmable and which may be electrically erased by the user.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, development of a semiconductor memory with large data storage capacity which can replace existing non-volatile data storage devices for digital computer systems, such as a magnetic floppy diskette drive unit, a fixed disk unit (also known as a "hard-disk drive unit"), or the like, has been demanded strongly.
To meet such requirement, specific electrically erasable and programmable read-only memories have been developed recently, which have been improved in their cell-packing density by decreasing the number of transistors required for each memory cell on a chip substrate of limited size. The memories may be referred to as the "EEPROM" in the present specification.
A very recent development has been the "NAND type EEPROM" which does not require the use of any extra transistor as a switching gate for each memory cell and thus can exhibit dramatic density improvement. With the NAND cell type EEPROM, series circuits of floating gate type metal oxide semiconductor field effect transistors, or MOSFETs, are arranged so that each series transistor circuit is connected with a corresponding one of data transfer lines through a single switching transistor. The data transfer lines may be called the "bit lines." When the switching transistor is rendered conductive, the series circuit of floating gate type MOSFETs associated therewith is connected selectively to the corresponding bit line. In this sense, the switching transistor is ordinarily called the "select transistor" among those skilled in the art.
Each of the series-arrayed floating gate type MOSFETs serves as a minimum element for digital data storage, which may be considered to correspond to a "memory cell" as in conventional dynamic random access memories or DRAMs. (In some cases, one series circuit of MOSFETs will be called a "memory cell." Such terminology itself is not so important. In this patent specification, each series array of MOSFETs will be named as a "NAND cell unit.") Generally, each transistor array includes four, eight or sixteen floating gate type MOSFETs. Each MOSFET has a control gate connected to a corresponding word line and a floating gate for storing carriers indicative of a logic "1" or "0." Since each memory cell can be formed of one floating gate type MOSFET, the integration density of the EEPROM can be enhanced and therefore the memory capacity thereof can be increased.
With the currently available NAND cell type EEPROM, data is sequentially written into the floating gate type MOSFETs, that is, memory cell transistors in each NAND cell unit. In a case where logic data is written into the EEPROM at a desired memory address, that is, into a selected one of the floating gate type MOSFETs of the designated NAND cell unit, a high voltage Vpp and an intermediate voltage are used. The high voltage is typically a 20-volt voltage; the intermediate voltage Vppm has a potential level between the power source voltage Vcc of the EEPROM and the high voltage Vpp and is typically at 10 volts when the power source voltage Vcc is 5 volts. The high voltage Vpp is applied to the control gate electrode of a selected memory cell transistor and the intermediate voltage Vppm is applied to the control gate electrodes of non-selected memory cell transistors lying between the selected memory cell transistor and the select transistor. The non-selected memory cell transistors are rendered conductive.
Under such condition, when a voltage representing the logic "1" data (typically, a zero-volt voltage) is given to a corresponding bit line, this data voltage is transferred to a target memory cell--more specifically, the drain layer of a selected floating gate type MOSFET--through the nonselected memory cell transistors that remain conductive. A high electric field is thus created between the floating gate electrode and the drain of the selected memory cell transistor. This results in that electrons are injected by tunneling effect from the substrate (drain) to the floating gate electrode. The threshold value of the selected memory cell transistor is shifted along the direction of positive polarity. The logic "1" data is stored ("programmed") at the desired cell address. When the intermediate voltage Vppm is applied as a voltage indicative of the logic "0" data to the bit line, the injection of electrons does not occur in the selected floating gate type MOSFET. The threshold value of this MOSFET is thus kept unchanged. This state is defined as the logic "0" data storing state.
The memory cell transistors in the NAND cell type EEPROM is simultaneously erased with a predetermined size of block being as a unit, which is generally the entire portion of one chip of the EEPROM is dealt as one block. This is so-called "simultaneous erasing." At this time, all of the NAND cell units of the EEPROM are electrically separated from the bit lines, the substrate and a common source voltage. The control gate electrodes of all the memory cell transistors are at 0 volts and the substrate voltage (and the well potential if the NAND cell units are formed in a well region) is set to be the high voltage Vpp. As a result, in all of the memory cell transistors, electrons are moved or released from the floating gate electrodes thereof to the substrate (or the well region). The threshold values thereof are shifted along the direction of negative polarity. The stored data items are electrically erased at the same time.
To read stored data selectively from a designated one of the memory cell transistors, a zero-volt voltage is applied to the control gate electrode of the selected memory cell transistor. The control gate electrodes of the remaining one of the memory cell transistors are at a power supply voltage Vcc (5 volts, for example). These nonselected transistors are rendered conductive due to the application of power supply voltage Vcc. Under such a condition, the logical value of the data stored in the selected memory cell transistor may be judged by sensing whether current flows in the common source line, which is also associated with specific NAND cell unit containing the selected memory cell transistor.
With the NAND cell type EEPROM mentioned above, the select transistors are being applied with the zero-volt voltage at their gate electrodes, while the substrate is applied with the high voltage Vpp in the data erase mode. A high electric field will be creased within gate insulation layers of the select transistors. After the above-mentioned simultaneous erasing is repeatedly executed, the gate insulation layers of the select transistors will be decreased in the dielectric breakdown characteristic, or withstanding voltage characteristic thereof. Once dielectric breakdown occurs in any one of the select transistors, effective data accessing performance will no longer be expected in the NAND cell type EEPROM. The same problem has been inherent in NOR cell type EEPROMs.